pulp-platform / common_cells

Common SystemVerilog components
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Width mismatch error in assign statement with VCS strict compile #191

Closed rsharanesh closed 8 months ago

rsharanesh commented 1 year ago

In the below assignment, the RHS being a genvar is 32-bits wide, while the LHS which is parameterized and need not be always of 32-bits wide. Thus the compiler throws a width mismatch error.

https://github.com/pulp-platform/common_cells/blob/0989ff73d0315922791bf42137c0ce0cbb4a76ca/src/onehot_to_bin.sv#L26

Can the code be modified to be generic enough with the assignment like this, assign tmp_i = i[BIN_WIDTH-1:0];