search

pulp-platform / common_cells

Common SystemVerilog components
Other
488 stars 138 forks source link

Add `mem_to_banks_detailed` #194

Closed micprog closed 1 year ago

micprog commented 1 year ago

Adds sideband data in the response path to be managed externally. mem_to_banks now wraps the mem_to_banks_detailed.

micprog commented 1 year ago

The updated mem_to_banks wrapper was tested with the axi_to_mem_banked testbench in the AXI repository, it still works as originally intended.