pulp-platform / common_cells

Common SystemVerilog components
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spill_register_flushable assertion improvement #197

Open tsyw opened 1 year ago

tsyw commented 1 year ago

When downstream has backpressure, the flush function cannot work properly. so can we add the following sva property? assupe property ( @(posedge clk_i) disable iff (!rst_ni) flush_i |-> ready_i ) else $warning("Trying to flush when downstream not ready");

tsyw commented 1 year ago

sorry for the typo: assume property ( @(posedge clk_i) disable iff (!rst_ni) flush_i |-> ready_i ) else $warning("Trying to flush when downstream not ready");