it seems that most of the modules in this repository exclude assertions when simulating with Verilator. Typically, the assertions are surrounded by an ifndef - endif block that excludes them in Verilator, such as for instance in the fifo_v3:
Verilator has had support for assert properties since at least version 3.922 released in 2018 and support for the implication operator has been added in version 4.026 released in 2020. AFAIK the initial block is a bit more of a recent addition, but has also been supported for a while now.
Is there a particular reason why assertions are excluded in Verilator (e.g., this repo must support some version of Verilator that cannot handle assert properties)? Could this restriction be lifted given the time that Verilator already has had support for this?
Hi,
it seems that most of the modules in this repository exclude assertions when simulating with Verilator. Typically, the assertions are surrounded by an
ifndef-endifblock that excludes them in Verilator, such as for instance in thefifo_v3:https://github.com/pulp-platform/common_cells/blob/2bd027cb87eaa9bf7d17196ec5f69864b35b630f/src/fifo_v3.sv#L141-L153
Verilator has had support for assert properties since at least version 3.922 released in 2018 and support for the implication operator has been added in version 4.026 released in 2020. AFAIK the initial block is a bit more of a recent addition, but has also been supported for a while now.
Is there a particular reason why assertions are excluded in Verilator (e.g., this repo must support some version of Verilator that cannot handle assert properties)? Could this restriction be lifted given the time that Verilator already has had support for this?