pulp-platform / common_cells

Common SystemVerilog components
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Remove wrappers #202

Open niwis opened 10 months ago

niwis commented 10 months ago

Several IPs internally instantiate a more generic version, leaving unneeded ports tied or unconnected. To ensure that only the required logic is instantiated, cross-boundary optimisations and constant propagation are needed, putting a lot of weight on the tools, which often do not meet expectations.

Therefore, restructure the IPs that currently rely on wrappers in a more tool-friendly manner (i.e. using parameters). These IPs are