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pulp-platform / common_cells

Common SystemVerilog components
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Found a bug in "stream_xbar" module when two different "sel_i" have same value #208

Closed mhayat-10xe closed 8 months ago

mhayat-10xe commented 8 months ago

I am working on "stream_xbar.sv" to verify it formally. I found one bug that when two different sel_i port have same destination then ready_o of these port can't be high at a same time. For example, if "sel_i[0] = 2" and "sel_i[3] = 2" then "ready_o[0]" and "ready_o[3]" can't be high at same time. Is this a bug or design intent?

niwis commented 8 months ago

Hello, the intent of stream_xbar is to arbitrate downstream slaves between masters. If two masters access the same slave in the same cycle, rr_arb_tree determines which master to serve. I hope this answers your question. @thommythomaso feel free to add/correct

mhayat-10xe commented 8 months ago

Hello Niwis,

There is still some confusion. Is it compulsory to have a ready_o high when two masters access the same slave?

For example, in the same cycle, if "sel_i[0]=2", "sel_i[1]=2", "valid_i[0]=1" and "valid_i[1]=1", then to access slave number 2, do ready_o[0,1] both have to be high at the same time or only one from these two will be high and other remain low?

niwis commented 8 months ago

Hi @hayat10x, I'm not sure if I understand your question correctly. A slave can only be accessed by one master at a time. if two masters (0, 1 in your example) request access to the same slave (2), they are arbitrated, and only one of the requests is granted at a time. Therefore, valid values for ready_o in your examples would be {0, 0}, {0, 1}, {1, 0} (not {1, 1})

mhayat-10xe commented 8 months ago

Hi Niwis, Thanks for the clarification.