Added macro with asynchronous reset and synchronous clear.

pulp-platform / common_cells

Common SystemVerilog components

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Added macro with asynchronous reset and synchronous clear. #214

Closed yvantor closed 6 months ago

yvantor commented 6 months ago

@niwis not putting this in draft state as I think it will not need much more than this, but I think it might make sense to wait for the activity on CVA6 to complete before evaluating a merge.