hi,
my ASIC library has synchronization flops which take two clocks and implement back-to-back flops. I'd like to be able to use these flops in the CDC implementation but alas the SYNC module implementation is not easy to modify for this purpose as it sees only one clock. Do you have any suggestions on how to replace the two flops which take two different clocks with a single cell such that the maxdelay constraint is automatically resolved ?
hi, my ASIC library has synchronization flops which take two clocks and implement back-to-back flops. I'd like to be able to use these flops in the CDC implementation but alas the SYNC module implementation is not easy to modify for this purpose as it sees only one clock. Do you have any suggestions on how to replace the two flops which take two different clocks with a single cell such that the maxdelay constraint is automatically resolved ?