Fixing the reset polarity of assertions in stream_xbar and stream_omega_net (#200) uncovered numerous assertion failures in our designs using common_cells. One assertion failure we observe may result from intentional, functionally correct design.
stream_xbar and stream_omega_net are commonly used for in-cycle banked SRAM interconnects (e.g. PULP TCDM), wherein parts of a valid payload may freely change if they are not relevant to that payload.
The most common example is a shared request channel for reads and writes. The write data is always part of the payload, but on reads (i.e. when the write enable in the payload is low), it is irrelevant to the request. Thus, efficient designs may opt to hardwire write data to a write-specific datapath, which may result in write data changes while a valid read request is pending.
While functionally harmless, such changes trigger the current data stability assertions in stream_xbar and stream_omega_net which provide either strict stability assertions on all payload bits (AxiVldRdy == 1) or no stability assertions at all (AxiVldRdy == 0).
This MR adds a mask parameter AxiVldMask allowing designers to choose on which payload bits stability should be asserted. Since the default mask is '1, this change is non-breaking.
bluewww
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5 months ago
Fixing the reset polarity of assertions in
stream_xbarandstream_omega_net(#200) uncovered numerous assertion failures in our designs usingcommon_cells. One assertion failure we observe may result from intentional, functionally correct design.stream_xbarandstream_omega_netare commonly used for in-cycle banked SRAM interconnects (e.g. PULP TCDM), wherein parts of a valid payload may freely change if they are not relevant to that payload.The most common example is a shared request channel for reads and writes. The write data is always part of the payload, but on reads (i.e. when the write enable in the payload is low), it is irrelevant to the request. Thus, efficient designs may opt to hardwire write data to a write-specific datapath, which may result in write data changes while a valid read request is pending.
While functionally harmless, such changes trigger the current data stability assertions in
stream_xbarandstream_omega_netwhich provide either strict stability assertions on all payload bits (AxiVldRdy == 1) or no stability assertions at all (AxiVldRdy == 0).This MR adds a mask parameter
AxiVldMaskallowing designers to choose on which payload bits stability should be asserted. Since the default mask is'1, this change is non-breaking.