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Common SystemVerilog components
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`stream_arbiter` with priority arbitration inherently violates assertion #221

Closed paulsc96 closed 2 months ago

paulsc96 commented 3 months ago

When configuring a stream_arbiter or stream_arbiter_flushable with ARBITER = "prio", it instantiates an rr_arb_tree with both the ExtPrio and LockIn parameters set:

https://github.com/pulp-platform/common_cells/blob/0d67563b6b592549542544f1abc0f43e5d4ee8b4/src/stream_arbiter_flushable.sv#L55-L61

However, this directly violates an assertion in rr_arb_tree:

https://github.com/pulp-platform/common_cells/blob/0d67563b6b592549542544f1abc0f43e5d4ee8b4/src/rr_arb_tree.sv#L319

As a result, any priority stream arbiters instantiated inherently cause a fatal assertion violation.