Open silabs-PaulZ opened 4 years ago
Several CSR mnemonics are incorrect. See the various requested fixes below.
I’m compiling with the following options for CV32E40P (aka RI5CY): -march=rv32imc -w -Os -g -nostdlib - -static -I $RISCV_TOOL_DIR/riscv32-unknown-elf/include -L $RISCV_TOOL_DIR/lib -lc -lm -lgcc Github tag: v1.0.16
(I would assume we want these all fixed regardless of being used in RI5CY or CV32E40P)
ustatus (note 1) uie utvec (note 1) uscratch uepc (note 1) ucause (note 1) utval uip mtval (note2) mcountinhibit (note 2) dscratch0 (note 3,note4) dscratch1 (note 3)
Note 1: Implemented in RI5CY, not needed for CV32E40P Note 2: Not implemented in RI5CY, will be needed for CV32E40P Note 3: Implemented in RI5CY and needed for CV32E40P Note 4: dscratchis implemented and maps to dscratch0
dscratch
dscratch0
lpstart0 0x800 lpend0 0x801 lpcount0 0x802 lpstart1 0x804 lpend1 0x805 lpcount1 0x806 mie1 0x7D0 mip1 0x7D1 uhartid 0xCC0 privlv 0xCC1 fprec 0x807 pcer_user 0xCC0 (note 5) pcmr_user 0xCC1 (note 5) pcer_machine 0x7E0 (note 5) pcmr_machine 0x7E1 (note 5) pccr0 0x780 (note 5) … pccr31 0x79F (note 5)
Note 5: These registers may not be needed in CV32E40P since replacing with RISC-V performance counters
csrr t2, hpmcounter16 -> csrr t2,privlv csrr t2, tselect -> csrr t2, pcer csrr t2, tdata1 -> csrr t2, pcmr csrr t2, dcsr -> csrr t2, lpstart0 csrr t2, dpc -> csrr t2, lpend0
csrr t2, fflags -> frflags t2 csrr t2, frm -> frrm t2 csrr t2, fcsr -> frsr t2 csrr t2, cycle -> rdcycle t2 csrr t2, time -> rdtime t2 csrr t2, instret-> rdinstret t2 csrr t2, cycleh -> rdcycleh t2 csrr t2, timeh -> rdtimeh t2 csrr t2, instreth-> rdinstreth t2
csrr t2, mhartid -> csrr t2, mhartid csrr t2, mstatus -> csrr t2, mstatus csrr t2, mtvec -> csrr t2, mtvec csrr t2, mepc -> csrr t2, mepc csrr t2, mcause -> csrr t2, mcause
For example, csrr t2, mie -> csrr t2, 0x304
csrr t2, mie -> csrr t2, 0x304
Several CSR mnemonics are incorrect. See the various requested fixes below.
I’m compiling with the following options for CV32E40P (aka RI5CY): -march=rv32imc -w -Os -g -nostdlib - -static -I $RISCV_TOOL_DIR/riscv32-unknown-elf/include -L $RISCV_TOOL_DIR/lib -lc -lm -lgcc Github tag: v1.0.16
FIX 1: Standard mnemonics not found:
(I would assume we want these all fixed regardless of being used in RI5CY or CV32E40P)
Note 1: Implemented in RI5CY, not needed for CV32E40P Note 2: Not implemented in RI5CY, will be needed for CV32E40P Note 3: Implemented in RI5CY and needed for CV32E40P Note 4:
dscratchis implemented and maps todscratch0FIX 2: Custom RI5CY/CV32E40P mnemonics not found
Note 5: These registers may not be needed in CV32E40P since replacing with RISC-V performance counters
FIX3: mnemonics that have incorrect names out of dissembler:
FIX4: mnemonics that have ‘slightly’ incorrect names out of dissembler:
OK: mnemonics that have correct names out of dissembler:
FIX5: The remaining mnemonics simply get converted to an address as opposed to mnemonics.
For example,
csrr t2, mie -> csrr t2, 0x304