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pulp-platform / pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
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Bender flow for FPGA #65

Closed micprog closed 2 years ago

micprog commented 2 years ago

This PR adds an updated flow for fpga deployment using bender, based on the implementation in https://github.com/pulp-platform/pulpissimo. Currently, only zcu102 is supported, but more can be easily added. The old files and flow using IPApproX is removed. This setup was tested on a zcu102 using an olimex debugger.

luca-valente commented 2 years ago

Ciao @micprog I'll dive into the commit later! Looks great so far. I have only one comment: the current flow (with all its limitations) currently supports both the zcu102 and the vcu118. I am not 100% convinced of removing the support for the vcu118. The only actual difference between the zcu102 and vcu118 is the xdc file and the BOARD variable when generating the clk_mngr and the boot_rom. Do you think it would make sense (or would be easy) to add preliminary support (no need to test the bitstream) for the vcu118? Just saying this to avoid regression on the FPGA emulation and losing the xdc. I am pretty confident that even if not tested the flow would work and I see no problem in writing a WIP disclaimer. Of course, we also have a vcu118 with the working setup in Bologna (debugger and so on...) and we could easily test it. Luca

micprog commented 2 years ago

Thanks @luca-valente for the feedback, of course adding support for the vcu118 makes sense, I have added the initial required files for bitstream generation.

luca-valente commented 2 years ago

Perfect! @OttG has the rights to merge. The PR looks good to me, the regressions passed and @micprog also executed the MobileNet on fpga.

OttG commented 2 years ago

@luca-valente if the xdc settings for the vcu118 are fine I think we can merge into master