This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
Upon my understanding PULP has three clock domains, one for the SoC (FC core, SoC memory, SoC interconnect), a second one for the SoC peripherals and the last for the cluster.
I was wondering what are the reasons for those multiple clock domains.
Would appreciate any answers or referral to documents that discuss this point.
Upon my understanding PULP has three clock domains, one for the SoC (FC core, SoC memory, SoC interconnect), a second one for the SoC peripherals and the last for the cluster. I was wondering what are the reasons for those multiple clock domains. Would appreciate any answers or referral to documents that discuss this point.