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pulp-platform / pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
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RTL Simulation platform build is failing #81

Closed prajwalkashyap closed 1 year ago

prajwalkashyap commented 1 year ago

I am trying to build RTL simulation platform. 

source setup/vsim.sh
make checkout
make scripts
make build

It is failing with below error

# ** Error: (vlog-13069) /test_folder/pulp/.bender/git/checkouts/pulp_cluster-34378b934f86e516/rtl/cluster_bus_wrap.sv(27): near "import": syntax error, unexpected import, expecting ';'.
# End time: 11:50:36 on May 16,2023, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# 1
#  quit
vopt +acc=npr -o vopt_tb tb_pulp -floatparameters+tb_pulp -work work
Model Technology ModelSim SE-64 vopt 10.4c Compiler 2015.07 Jul 19 2015
Start time: 11:50:37 on May 16,2023
vopt "+acc=npr" -o vopt_tb tb_pulp -floatparameters+tb_pulp -work work 

Top level modules:
    tb_pulp

Analyzing design...
** Error: (vopt-13130) Failed to find design unit work.tb_pulp.
Optimization failed
End time: 11:50:37 on May 16,2023, Elapsed time: 0:00:00
Errors: 1, Warnings: 0
make[1]: *** [Makefile:41: opt] Error 2

Does anybody know why this occurs ?

bluewww commented 1 year ago

You need questasim (newer version of modelsim). You are using an older modelsim which doesn't support enough of SystemVerilog 2017.

sjl821 commented 5 months ago

I have installed ModelSim SE 2020.4, but I encoutered the same error.