This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
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Attaching an IP in cluster_bus within pulp_cluster #86
Hi,
As mentioned in https://github.com/pulp-platform/pulp/issues/83 , I am trying to add an IP using axi to cluster_bus_wrap. My IP has an axi data width of 32-bit. I see that axi_xbar within cluster_bus is using 64-bit data width. I added an AXI_BUS.Master to cluster_bus_wrap module . However, I am unable to specify the data-width either in cluster_bus_wrap module declaration or within cluster_bus_wrap for axi_xbar. I think this is preventing me from transferring data correctly to my IP. How can I create an AXI_BUS.Master interface in cluster_bus_wrap module declaration with 32-bit data and while mapping axi_masters in axi_xbar within cluster_bus_wrap?
Hi, As mentioned in https://github.com/pulp-platform/pulp/issues/83 , I am trying to add an IP using axi to cluster_bus_wrap. My IP has an axi data width of 32-bit. I see that axi_xbar within cluster_bus is using 64-bit data width. I added an AXI_BUS.Master to cluster_bus_wrap module . However, I am unable to specify the data-width either in cluster_bus_wrap module declaration or within cluster_bus_wrap for axi_xbar. I think this is preventing me from transferring data correctly to my IP. How can I create an AXI_BUS.Master interface in cluster_bus_wrap module declaration with 32-bit data and while mapping axi_masters in axi_xbar within cluster_bus_wrap?