This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
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add fast L2 preload, FPGA flashing targets and FPGA Readme info #88
I copied Manuel's "fast L2 preloading" from Pulpissimo, which can be activated by passing the LOAD_L2=FAST_DEBUG_PRELOAD parameter and drastically reduces the simulation wait time for loading code into L2
I added targets for flashing FPGA boards (flash_zcu102/flash_vcu118) and added some more information to the FPGA README.
FPGA stuff has been tested on ZCU102.
As the name says:
LOAD_L2=FAST_DEBUG_PRELOADparameter and drastically reduces the simulation wait time for loading code into L2flash_zcu102/flash_vcu118) and added some more information to the FPGA README. FPGA stuff has been tested on ZCU102.