Reduce Latency in AXI Crossbar of SoC interconnect and AXI-Lite to APB Bridge

pulp-platform / pulp_soc

pulp_soc is the core building component of PULP based SoCs

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Reduce Latency in AXI Crossbar of SoC interconnect and AXI-Lite to APB Bridge #64

Closed meggiman closed 3 years ago

meggiman commented 3 years ago

This change reduces the pipeline stages in the AXI crossbar and axi-lite to APB peripheral. This reduces FC/uDMA to peripheral/cluster latency by 3 cycles.

meggiman commented 3 years ago

This commit should be merged after #63

bluewww commented 3 years ago

lgtm