The fpga ports no longer need out-context synthesis of the Xilinx SRAM IPs.
Instead the tech_cells_generic tc_sram wrapper will instantiate a xilinx
parametrized macro (if bender/IPapprox is given the right target). This way, we
no longer need to manually sync SRAM memory size between RTL and FPGA tcl scripts.
meggiman
commented
3 years ago
The fpga ports no longer need out-context synthesis of the Xilinx SRAM IPs. Instead the tech_cells_generic tc_sram wrapper will instantiate a xilinx parametrized macro (if bender/IPapprox is given the right target). This way, we no longer need to manually sync SRAM memory size between RTL and FPGA tcl scripts.