Hi everyone,
I am implementing the pulpissimo project. I synthesize it with "SYNTHESIS" and "TARGET_SYNTHESIS" defined. This leads to the signals of s_stdout_bus to be forced to low in the soc_peripherals (specifically pready, pslverr and prdata ). I use genus as synthesis tool and it correctly then warns about the signals being multidriven.
Can you expand on the reasoning why these signals are special and why they are pulled low?
Warning : Signal or variable has multiple drivers, including a constant driver. [CDFG2G-623]
: 's_stdout_bus_pready' in module 'soc_peripherals_MEM_ADDR_WIDTH17_APB_ADDR_WIDTH32_APB_DATA_WIDTH32_NB_CORES0_NB_CLUSTERS0_EVNT_WIDTH8_NGPIO32_NPAD64_NBIT_PADCFG6_NBIT_PADMUX2_N_UART32h00000001_N_SPI32h00000001_N_I2C32h00000002_SIM_STDOUT0_apb_slave_APB_BUS_Slave_apb_eu_master_APB_BUS_Master_apb_hwpe_master_APB_BUS_Master_apb_debug_master_APB_BUS_Master_l2_rx_master_XBAR_TCDM_BUS_Master_l2_tx_master_XBAR_TCDM_BUS_Master_soc_fll_master_FLL_BUS_out_per_fll_master_FLL_BUS_out_cluster_fll_master_FLL_BUS_out' in file '/home/lanius/code/pulp/pulpissimo/.bender/git/checkouts/apb-b24fbe74bd47ac2e/src/apb_intf.sv' on line 26, column 38.
: Some tools may not accept this HDL.
Hi everyone, I am implementing the pulpissimo project. I synthesize it with "SYNTHESIS" and "TARGET_SYNTHESIS" defined. This leads to the signals of
s_stdout_bus
to be forced to low in the soc_peripherals (specifically pready, pslverr and prdata ). I use genus as synthesis tool and it correctly then warns about the signals being multidriven. Can you expand on the reasoning why these signals are special and why they are pulled low?Kind regards Christian