atraber
commented
8 years ago Hi David
We use an AXI bus as our central interconnect and have a bridge to APB for peripherals. Our peripherals are rather low-speed and thus it makes sense to for APB because of its smaller size (less registers needed to store data). See also the block diagram: pulpino_block.pdf
Currently we don't have plans to add an SDRAM or DDR interface. For a DDR interface we would need a DDR phy which is something we do not have. DDR phys are very complex to create and the phy alone would be multiple times the size of a whole PULPino chip. Another problem with DDR phys is that they are technology dependent because they contain a lot of analog components. SDRAM is simpler to do, but you need lots of pins (same is true for DDR, btw). For the first PULPino chip we taped out (Imperio, see http://asic.ee.ethz.ch/2015/Imperio.html), we were already pad-limited with only 40 pins. Considering that you need much more pins for a useful SDRAM interface, it is not very realistic to do at the moment. We would need to go for much bigger chips.
Btw, if you have questions you can also send them to pulp@ethz.ch
Cheers Andy
davidfongsj1108
Hi,
For your brief description below about the peripherals:
"For communication with the outside world, PULPino contains a broad set of peripherals, including I2S, I2C, SPI and UART. The platform internal devices can be accessed from outside via JTAG and SPI which allows pre-loading RAMs with executable code. In standalone mode, the platform boots from an internal boot ROM and loads its program from an external SPI flash."
How are the peripherals communicating with the RISCV? Is it through AHB or AXI interface?
Also, do you plan to support larger and faster external memories like SDRAM or DDR via an AXI interface?