JTAG burst write to AXI via Advanced Debugging Unit skips odd words

[barrydebruin]

Hi,

While trying to initialize my DMEM content using JTAG I ran into an issue. You should be able to reproduce the problem with the default testbench using the following lines:

addr = 32'h0010_0000; // start of DMEM
adv_dbg_if.axi_write(5'h3, addr, 4, data_mem); // 32b writes, 4 words

If we now start an RTL simulation, we see that the first write is successfully written into DMEM, the second write is skipped, the third one is successfully written to DMEM, the fourth one is skipped, and so on.

With some further investigation, it seems that the odd writes due to the fact that strobe_i && rdy_o (adbg_axi_biu.sv) is not valid during odd writes (rdy_o is just too late).

I have attached a trace to show the exact situation:

[barrydebruin]

Problem on arises when system clock is equal to JTAG clock, which is not a realistic case. I consider this problem solved.