the enviornment variables XILINX_BOARD and XILINX_PART

[sofchet]

I am not sure what I should set XILINX_BOARD to ? I am using a zybo whose part number is xc7z010clg400-1 since I didn't find the XILINX_BOARD value for my board I just kept the default one ( em.avnet.com:zynq:zed:c ). After running the "make all" command everything seems to go well with no errors, but than at the end I get the following error:

synth_design completed successfully synth_design: Time (s): cpu = 00:05:03 ; elapsed = 00:05:06 . Memory (MB): peak = 1036.875 ; gain = 836.324 INFO: [Coretcl 2-1174] Renamed 8 cell refs. report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 1036.875 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Wed Oct 17 00:46:36 2018... [Wed Oct 17 00:46:39 2018] xilinx_clock_manager_synth_1 finished wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:05:15 . Memory (MB): peak = 236.441 ; gain = 5.879 INFO: [Common 17-206] Exiting Vivado at Wed Oct 17 00:46:39 2018... **mkdir -p ip A subdirectory or file ip already exists. Error occurred while processing: ip. make[1]: *** [all] Error 1 make[1]: Leaving directoryC:/pulpino/fpga/ips/xilinx_clock_manager' make: * [ips/xilinx_clock_manager/ip/xilinx_clock_manager.dcp] Error 2`

I am not sure whether it's related to something else, or it's just due to XILINX_BOARD and XILINX_PART.

ps: I removed the ip folder and tried again but still have the same issue

[sunil3690]

please add Vivado toolchain path and ri5cy_gnu_toolchain path before typing the command "make all" also make sure that u have licensed Vivado version 2015.1