stefanct
commented
5 years ago This looks to me as if your mkdir is not POSIX compatible or ip exists as a file for some reason. mkdir -p ip should not produce an error if a directory named ip exists according to POSIX.
Hi, I am trying to get the pulpino implemented on a Zybo, I followed all the steps in the FPGA directory. everything seems to work correctly when I enter the command "make all", even the synthesis is done successfully. But I always get at the end the following error :
INFO: [Common 17-83] Releasing license: Synthesis 188 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:05:03 ; elapsed = 00:05:06 . Memory (MB): peak = 1036.875 ; gain = 836.324 INFO: [Coretcl 2-1174] Renamed 8 cell refs. report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 1036.875 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Wed Oct 17 00:46:36 2018... [Wed Oct 17 00:46:39 2018] xilinx_clock_manager_synth_1 finished wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:05:15 . Memory (MB): peak = 236.441 ; gain = 5.879 INFO: [Common 17-206] Exiting Vivado at Wed Oct 17 00:46:39 2018... mkdir -p ip A subdirectory or file ip already exists. Error occurred while processing: ip. make[1]: *** [all] Error 1 make[1]: Leaving directoryC:/pulpino/fpga/ips/xilinx_clock_manager' make: *** [ips/xilinx_clock_manager/ip/xilinx_clock_manager.dcp] Error 2 ` do you have any idea why I am getting such error ?Thanks