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pulp-platform / pulpino

An open-source microcontroller system based on RISC-V
http://www.pulp-platform.org
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Pulpino Synthesis #320

Open aabimbar opened 5 years ago

aabimbar commented 5 years ago

Hello,

I have been trying to do an ASIC synthseis of Pulpino but I am facing some difficulties doing so. Mainly I am getting this error in Design Compiler:

Information: /home/aabimbar/pulpino/rtl/axi_node_intf_wrap.sv:14: Port .slave()'s array bounds [3:0] were translated to [0:3] by renaming at the module boundary (ELAB-123) Information: /home/aabimbar/pulpino/rtl/axi_node_intf_wrap.sv:14: Port .master()'s array bounds [3:0] were translated to [0:3] by renaming at the module boundary (ELAB-123) Error: /home/aabimbar/pulpino/rtl/axi_node_intf_wrap.sv:157: Array index out of bounds master[0].aw_id[11:0], valid bounds are [9:0]. (ELAB-298)

While compiling axi_node_intf_wrap.sv file.

I was hoping someone here could help me figure it out. Also I am suspecting that I may not be reading all the rtl files or maybe I am not reading it in the right order. Is there any way I could know what all files are to read?

Thanks!

aignacio commented 5 years ago

To get all IPs to build pulpino you should run ./update-ips.py in the root folder where the python script will read and catch all files needed. Pls check to read the main README again and see if you miss some step.