Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_controller.sv(534): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_controller.sv(33): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_debug_unit.sv(481): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_debug_unit.sv(486): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_debug_unit.sv(29): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_id_stage.sv(775): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_id_stage.sv(784): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_id_stage.sv(788): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_if_stage.sv(273): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_if_stage.sv(32): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_load_store_unit.sv(487): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_load_store_unit.sv(491): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_load_store_unit.sv(494): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_fetch_fifo.sv(228): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
** Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_fetch_fifo.sv(26): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
Failed to open executable /home/hou/Expand/intelFPGA_lite/19.1/modelsim_ase/linuxaloem/../linux_x86_64pe/vlog in execute mode needed for the option -64.
CMakeFiles/vcompile.dir/build.make:57: recipe for target 'CMakeFiles/vcompile' failed
make[3]: [CMakeFiles/vcompile] Error 1
CMakeFiles/Makefile2:168: recipe for target 'CMakeFiles/vcompile.dir/all' failed
make[2]: [CMakeFiles/vcompile.dir/all] Error 2
CMakeFiles/Makefile2:175: recipe for target 'CMakeFiles/vcompile.dir/rule' failed
make[1]: [CMakeFiles/vcompile.dir/rule] Error 2
Makefile:168: recipe for target 'vcompile' failed
make: [vcompile] Error 2
Does it mean the Altera starter edition ModelSim is not the correct version for simulation?
OS: Ubuntu 16.04
$make vcompile
.....
--> Compiling zero_riscy... Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 vmap zero_riscy_lib /home/hou/expand1/pulpino/vsim/modelsim_libs/zero_riscy_lib Modifying modelsim.ini Compiling component: zeroriscy
Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_controller.sv(534): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_controller.sv(33): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_debug_unit.sv(481): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_debug_unit.sv(486): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_debug_unit.sv(29): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_id_stage.sv(775): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_id_stage.sv(784): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_id_stage.sv(788): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_if_stage.sv(273): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_if_stage.sv(32): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_load_store_unit.sv(487): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_load_store_unit.sv(491): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_load_store_unit.sv(494): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_fetch_fifo.sv(228): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. ** Warning: /home/hou/expand1/pulpino/vsim/..//ips/zero-riscy/zeroriscy_fetch_fifo.sv(26): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim.
......
--> Compiling work.tb... Compiling component: work.tb
Failed to open executable /home/hou/Expand/intelFPGA_lite/19.1/modelsim_ase/linuxaloem/../linux_x86_64pe/vlog in execute mode needed for the option -64.
CMakeFiles/vcompile.dir/build.make:57: recipe for target 'CMakeFiles/vcompile' failed make[3]: [CMakeFiles/vcompile] Error 1 CMakeFiles/Makefile2:168: recipe for target 'CMakeFiles/vcompile.dir/all' failed make[2]: [CMakeFiles/vcompile.dir/all] Error 2 CMakeFiles/Makefile2:175: recipe for target 'CMakeFiles/vcompile.dir/rule' failed make[1]: [CMakeFiles/vcompile.dir/rule] Error 2 Makefile:168: recipe for target 'vcompile' failed make: [vcompile] Error 2
Does it mean the Altera starter edition ModelSim is not the correct version for simulation?