Closed SubhamRath closed 3 years ago
Hello , We are new and we are trying to implement pulpino on Arty-A7 35t FPGA board. Can any one suggest a proper flow from generation of RTL to application development ? We are using Vivado 2015.1 . Please help us to get it right. Thank You
https://github.com/aignacio/riscv_verilator_model
Hello , We are new and we are trying to implement pulpino on Arty-A7 35t FPGA board. Can any one suggest a proper flow from generation of RTL to application development ? We are using Vivado 2015.1 . Please help us to get it right. Thank You