We are trying to create a SystemC TLM model of PulpIssimo. We referred to the following paper for understanding the uDMA(micro-DMA) I/O subsystem, as we are not able to find much info about it in the datasheet.
Is the implementation of uDMA subsystem is as per the paper referred in PulpIssimo github repository?
http://ieeexplore.ieee.org/document/8106971/
There are further queries regarding uDMA subsystem -
Which files in github we can refer to, to understand interface between I/O peripherals and uDMA? We want to understand if handshaking interface signals are exactly as referred in paper?
What arbitration scheme is used by uDMA, to arbitrate among RX or TX channels?
uDMA subsystem should signal the core that a DMA transfer is complete. What interrupt interface does it use for the purpose? In general, what is interrupt interface between the uDMA (or SOC) subsystem and core (or processing) subsystem?
Datasheet for pulpIssimo refers to a Event/Interrupt controller, which sends interrupt to the core? Here, what does these interrupt IDs correspond to - dma_pe_evt_i and dma_pe_irq_i? Which of this is used to signal core that DMA transfer is complete?
Where can I find code (for reference) for uDMA subsystem, SOC Event Generator, Interrupt Controller etc?
Regards
Pratibha
Hi,
We are trying to create a SystemC TLM model of PulpIssimo. We referred to the following paper for understanding the uDMA(micro-DMA) I/O subsystem, as we are not able to find much info about it in the datasheet. Is the implementation of uDMA subsystem is as per the paper referred in PulpIssimo github repository? http://ieeexplore.ieee.org/document/8106971/
There are further queries regarding uDMA subsystem - Which files in github we can refer to, to understand interface between I/O peripherals and uDMA? We want to understand if handshaking interface signals are exactly as referred in paper? What arbitration scheme is used by uDMA, to arbitrate among RX or TX channels? uDMA subsystem should signal the core that a DMA transfer is complete. What interrupt interface does it use for the purpose? In general, what is interrupt interface between the uDMA (or SOC) subsystem and core (or processing) subsystem? Datasheet for pulpIssimo refers to a Event/Interrupt controller, which sends interrupt to the core? Here, what does these interrupt IDs correspond to - dma_pe_evt_i and dma_pe_irq_i? Which of this is used to signal core that DMA transfer is complete? Where can I find code (for reference) for uDMA subsystem, SOC Event Generator, Interrupt Controller etc? Regards Pratibha