Cannot generate VCD file

[Merok]

Hello,

I am trying to obtain the VCD file from an execution of a the hello example code in the Simple Runtime using the Ibex (formely zero-riscy) core.

I run my code using make run vsim/script=export_run.tcl but cannot find the VCD in build/<SRC_FILE_NAME>/pulpissimo/export.vcd.gz.

Here is the log I have:

$ make run vsim/script=export_run.tcl
/myvolume/pulpissimo/pulp-runtime/bin/stim_utils.py --binary=/myvolume/pulpissimo/pulp-runtime-examples/hello/build/test/test --vectors=/myvolume/pulpissimo/pulp-runtime-examples/hello/build/vectors/stim.txt
Created stimuli generator
  Added binary: /myvolume/pulpissimo/pulp-runtime-examples/hello/build/test/test
  Handling section (base: 0x1c000004, size: 0x120)
  Init section to 0 (base: 0x1c000124, size: 0x830)
  Handling section (base: 0x1c008000, size: 0x47c)
  Generating to file: /myvolume/pulpissimo/pulp-runtime-examples/hello/build/vectors/stim.txt
/myvolume/pulpissimo/pulp-runtime/bin/plp_mkflash  --flash-boot-binary=/myvolume/pulpissimo/pulp-runtime-examples/hello/build/test/test  --stimuli=/myvolume/pulpissimo/pulp-runtime-examples/hello/build/vectors/qspi_stim.slm --flash-type=spi --qpi
/myvolume/pulpissimo/pulp-runtime/bin/slm_hyper.py  --input=/myvolume/pulpissimo/pulp-runtime-examples/hello/build/vectors/qspi_stim.slm  --output=/myvolume/pulpissimo/pulp-runtime-examples/hello/build/vectors/hyper_stim.slm
cd /myvolume/pulpissimo/pulp-runtime-examples/hello/build && export VSIM_RUNNER_FLAGS='+ENTRY_POINT=0x1c008080 -dpicpppath /usr/bin/g++ -permit_unmatched_virtual_intf -gBAUDRATE=115200 -gLOAD_L2=JTAG' && vsim -64 -c -do 'source /myvolume/pulpissimo/sim/tcl_files/config/run_and_exit.tcl' -do 'source /myvolume/pulpissimo/sim/tcl_files/run.tcl; run_and_exit;'
Reading pref.tcl

# 2020.4

# source /myvolume/pulpissimo/sim/tcl_files/config/run_and_exit.tcl
# source /myvolume/pulpissimo/sim/tcl_files/run.tcl
# vsim -c -quiet vopt_tb -L models_lib -L vip_lib -t ps "+nowarnTRAN" "+nowarnTSCALE" "+nowarnTFMPC" "+TB_PATH=/myvolume/pulpissimo/sim/../../fe/tb/" "+UVM_NO_RELNOTES" "+ENTRY_POINT=0x1c008080" -dpicpppath /usr/bin/g++ -permit_unmatched_virtual_intf "+VSIM_PATH=/myvolume/pulpissimo/sim" -gUSE_SDVT_SPI=0 -gUSE_SDVT_CPI=0 -gBAUDRATE=115200 -gENABLE_DEV_DPI=0 -gLOAD_L2=JTAG -gUSE_SDVT_I2S=0 
# Start time: 13:22:50 on Oct 08,2021
# //  Questa Sim-64
# //  Version 2020.4 linux_x86_64 Oct 13 2020
# //
# //  Copyright 1991-2020 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# ** Warning: (vsim-3770) Failed to find user specified function 'jtag_tick' in DPI C/C++ source files.
#    Time: 0 ps  Iteration: 0  Region: /SimJTAG_sv_unit File: /myvolume/pulpissimo/sim/../rtl/tb/SimJTAG.sv
# ** Warning: (vsim-8683) Uninitialized out port /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fll_soc/i_FLL_digital/TQ has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized out port /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fll_soc/i_FLL_digital/JTQ has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized out port /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fll_per/i_FLL_digital/TQ has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized out port /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fll_per/i_FLL_digital/JTQ has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized out port /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fll_cluster/i_FLL_digital/TQ has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8683) Uninitialized out port /tb_pulp/i_dut/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fll_cluster/i_FLL_digital/JTQ has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-3040) Command line generic/parameter "USE_SDVT_I2S" not found in design.
# ** Warning: (vsim-3040) Command line generic/parameter "USE_SDVT_SPI" not found in design.
#  run_and_exit
# [CORE] Core settings: PULP_SECURE =           1, N_PMP_ENTRIES =          16, N_PMP_CFG           4
# [TB]       0ns - Entry point is set to 0x1c008080
# [TB]       0ns - Asserting hard reset
# [TB]       1ns - Using FLL
# [TB]       1ns - Not using CAM SDVT
# Loading default stimuli
# [JTAG] SoftReset Done(    701ns)
# [JTAG] Bypass Test Passed (  33301ns)
# [JTAG] Tap ID: 249511c3 (  43701ns)
# [JTAG] Tap ID Test PASSED (  43701ns)
# [test_mode_if]   50301ns - Init
# [TB]   50301ns - Enabling clock out via jtag
# [test_mode_if]   51801ns - Setting confreg to value 002.
# [TB]   51801ns - jtag_conf_reg set to 002
# [TB]   51801ns - Releasing hard reset
# [TB]   53401ns - Init PULP TAP
# [pulp_tap_if] WRITE32 burst @1c008080 for           4 bytes.
# [TB]   67501ns - Write32 PULP TAP
# [JTAG] R/W test of L2 succeeded
# [TB]  177701ns - Halting the Core
# [TB]  236501ns - Writing the boot address into dpc
# [TB]  280601ns - Loading L2 via JTAG
# [JTAG] Loading L2 with pulp tap jtag interface
# [pulp_tap_if] WRITE32 burst @1c000000 for        1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c000400 for        1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c000800 for         344 bytes.
# [pulp_tap_if] WRITE32 burst @1c008000 for        1024 bytes.
# [pulp_tap_if] WRITE32 burst @1c008400 for         128 bytes.
# [TB] 3173501ns - Resuming the CORE
# [TB] 3217601ns retrying debug reg access
# [TB] 3246901ns retrying debug reg access
# [TB] 3276201ns retrying debug reg access
# [TB] 3305501ns retrying debug reg access
# [TB] 3334801ns retrying debug reg access
# [TB] 3364101ns retrying debug reg access
# [TB] 3393401ns retrying debug reg access
# [TB] 3422701ns retrying debug reg access
# [TB] 3452001ns retrying debug reg access
# [TB] 3481301ns retrying debug reg access
# [TB] 3510601ns retrying debug reg access
# [TB] 3539901ns retrying debug reg access
# [TB] 3569201ns retrying debug reg access
# [TB] 3598501ns retrying debug reg access
# [TB] 3627801ns retrying debug reg access
# [TB] 3657101ns retrying debug reg access
# [TB] 3686401ns retrying debug reg access
# [TB] 3715701ns retrying debug reg access
# [TB] 3745001ns retrying debug reg access
# [TB] 3774301ns retrying debug reg access
# [TB] 3803601ns retrying debug reg access
# [TB] 3832901ns retrying debug reg access
# [TB] 3862201ns retrying debug reg access
# [TB] 3891501ns retrying debug reg access
# [TB] 3920801ns retrying debug reg access
# [TB] 3950101ns retrying debug reg access
# [STDOUT-CL31_PE0] Hello !
# [TB] 4523501ns - Waiting for end of computation
# [TB] 4617601ns - Received status core: 0x00000000
# ** Note: $stop    : /myvolume/pulpissimo/sim/../rtl/tb/tb_pulp.sv(857)
#    Time: 4617601 ns  Iteration: 0  Instance: /tb_pulp
# Break in Module tb_pulp at /myvolume/pulpissimo/sim/../rtl/tb/tb_pulp.sv line 857
# Stopped at /myvolume/pulpissimo/sim/../rtl/tb/tb_pulp.sv line 857
# End time: 13:23:16 on Oct 08,2021, Elapsed time: 0:00:26
# Errors: 0, Warnings: 9

Could you help me ?

Best

[Merok]

Hi,

Any help on this issue would be greatly appreciated.

Thanks for the help.

[meggiman]

We normally generate VCDs using the simulator console directly. Looking at the console output that seems to work fine on you side. So you can start the simulation in interactive GUI mode (make run gui=1) and then use Questasim to generate the VCD using the following commands:

vcd file <path_where_you_want_the_vcd_to_be_stored.vcd>
vcd add -r <whatever module you are interested in>
run -all
vcd flush

[Merok]

Thank you for your reply. Could you tell me where the list of modules are (i.e to look for the execution block)?

Thanks for you help.

[meggiman]

What modules do you mean? You have to look at the RTL source code yourself to figure out which signals you want to add to the VCD.

[Merok]

I want to generate the vcd only for a specific module. For example, to target the ALU of ibex, I tried to specify vcd add -r /pulpissimo/ips/ibex/rtl/ibex_ex_block.sv but I obtain an error: # ** UI-Msg (suppressible): (vsim-3561) No objects found matching 'ibex_ex_block'.

I am new to modelsim so maybe this is not the correct way to do it. Do you have insight on how I should proceed ?

Thanks for the help.

[meggiman]

Hi @Merok

Please read up on how to use the VCD commands in the Questa user manual. Conceptually it is wrong to try vcd dumping a systemverilog file. You can dump VCD on module instances thus you must provide a hierarchical path for the design instance of interest to the vcd add command. Consider the case where you have a design with more than one ibex core; how should questasim know which instance of the core you want to generate traces for if you just provide a file name?