meggiman
commented
2 years ago Hi @yttuncel, I don't know what you mean with "soft implementations" but for an actual ASIC tapeout you would have to replace the clock generators with corresponding analog IPs (PLLs or FLLs) or modify the RTL to supply the clock externally if speed and power is of no significance for your project. Also you would have to map the technology dependent primitave tech cells in the tech_cells_generic repository to your target technology. This repository contains wrappers for integrated glitch-free clock gating cells (ICGs), clock multiplexers and IO pad cells etc. On top of that you most certainly want to replace the memories within PULPissimo with SRAM macros from your target tech. These are the most important IPs that come to my mind that need replacement. However, every tape-out is different and requires you to be fully familiar with the design and the target technology to be successful. Best, Manuel
Hi all,
After a looong time spent on ironing-out some issues, I finally have a working PULPissimo based SoC with 5 hardware accelerators. I've implemented a few applications so far with the design, and on FPGA I see close to 10x higher energy efficiency. I'd like to thank you for making this possible! :)
As the next step, I'm planning to tape-out this design. As far as I know, the xilinx clock manager IPs should be replaced with soft implementations. However, I'm not sure what else exactly needs to be changed (e.g. are there other ips that I'm not aware of, such as IO or memory?). Could you please provide some information/pointers regarding this?
PS: I know this might depend on the particular tech library that I use. Unfortunately I'm still in the process of getting my hands on a PDK, but for the sake of discussion let's assume I use TSMC65LP.
Best, Yigit