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pulp-platform / pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
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Mapping Error in DC #335

Closed Ahmedsaied9 closed 2 years ago

Ahmedsaied9 commented 2 years ago

When running Compile command in DC i get this error.

image

any clue how to solve this?

christian-lanius commented 2 years ago

The FLL in general can not be synthesized as far as I am aware, if you check @meggiman comment on doing an ASIC implementation here in #292. The digital part should be synthesizable though, so keep that in mind. In this specific case, the SelB_SP register is an asynchronous reset, falling edge sensitive flipflop. If your library does not have such a register, you might observe this error. One possible fix would be to manually instantiate an inverter cell in the clock path and then use a rising edge FF. You can instruct DC to do this automatically (according to the internet), if you check this comment here:

If you want to allow mapping to a library register with the opposite clock/enable phase, then you can use the variable compile_automatic_clock_phase_inference to alter the way that mapping operates. Setting this variable to “none” will instruct the tool to ignore clock phase and allow mapping to registers with both positive and negative clock/enable phase as needed. Setting this variable to “relaxed” will instruct the tool to only try the opposite phase device if there is no other way to implement the register with the automatically inferred phase. And, setting the variable to “strict” (the default setting) will instruct the tool to reject all library cells whose clock/enable phase does not match the automatically inferred phase.