Closed ivanhira closed 1 year ago
Can you describe your debugging process? I can debug normally here. I haven't encountered anything like you
Hi, sorry for the late reply.
It was actually a change in the RTL where a module soc_interconnect_wrap was running with peripheral clock instead of the core clock. It was committed by accident by someone, and it wasn't detected in the simulation because they were the same frequency.
Thanks for helping.
Hi @ivanhira I am facing the same issue. How did you fix the error? In the RTL, I can see that soc_interconnect_wrap is not running with the peripheral clock.
Hi @ivanhira, @prajwalkashyap I am facing the same issue. How did you fix the error?
Hi,
I'm trying to test the SoC on a Nexys Video FPGA. When I try to run OpenOCD after loading the bitstream to the FPGA, the following error occurs:
I guess I should mention that I'm using Debian 10 VM on Virtualbox, and the USB seems to work just fine. I did load the bitstream using Vivado from the VM to the FPGA, and the device shows up when running
lsusb
.The RTL is modified: I removed the FLLs and created PADs for external clock signals, because we didn't have FLL cells to synthesize it. I had to modify the kernel to not initialize the flls, but in the simulation it worked great. I don't think this is the reason it fails, because there is an FPGA FLL that is instantiated when building for FPGAs. But that is the only change in the RTL made.
Also, in the
pulp_soc.sv
file, thedm_top
module has the portdmactive_o
connected to nothing. Is that correct? There's a comment that says "active debug session" that I don't know what it means.What could be the problem and solution to this?
Thanks in advance.