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pulp-platform / pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
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Bitstream Generation Error #388

Open Simon149 opened 1 year ago

Simon149 commented 1 year ago

Hi I am working on FPGA Nexys4 A7-100T and 35T . There are two errors when I generate ibex bitstreamfile. No matter which Nexys FPGA board I choose, I will receive the same error message.

Here are some information from my side. Vivado version: 2020.2 OS:Ubuntu 20.04

Terminal message:

read_ip $FPGA_IPS/xilinx_clk_mngr/xilinx_clk_mngr.srcs/sources_1/ip/xilinx_clk_mngr/xilinx_clk_mngr.xci ERROR: [Vivado 12-172] File or Directory '/home/user/PULP/pulpissimo/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/xilinx_clk_mngr.srcs/sources_1/ip/xilinx_clk_mngr/xilinx_clk_mngr.xci' does not exist INFO: [Common 17-206] Exiting Vivado at Fri Mar 17 16:41:00 2023... make[1]: [Makefile:14: all] Error 1 make[1]: Leaving directory '/home/user/PULP/pulpissimo/fpga/pulpissimo-nexys' make: [Makefile:53: nexys] Error 2

How do I fix the error? Thanks

gyx3598 commented 1 year ago

Customized clock IP can solve the problem

haresh-seenivasagan commented 10 months ago

hi @gyx3598 i am a beginner. If you dont mind could go in a bit more detail about how i can create a customized clock IP and how to tackle this issue

l1onog commented 6 months ago

I am experiencing the same problem, how can the problem be solved?