Closed zealshah29 closed 5 months ago
l1onog
commented
5 months ago hi, @zealshah29 ,How did you download and compile openocd, when I run the "openocd -f /opt/riscv/pulp/fpga/pulp-zcu102/openocd-zcu102-digilent-jtag-hs2.cfg" command, the error "Debug Module did not become active. dmcontrol=0x0" always appears, which bothers me a lot.
zealshah29
commented
5 months ago hi, @zealshah29 ,How did you download and compile openocd, when I run the "openocd -f /opt/riscv/pulp/fpga/pulp-zcu102/openocd-zcu102-digilent-jtag-hs2.cfg" command, the error "Debug Module did not become active. dmcontrol=0x0" always appears, which bothers me a lot.
Hi @l1onog,
So I followed the steps mentioned in the pulpissimo readme file under openocd and gdb section. First I installed the following modules: • autoconf >= 2.64 • automake >= 1.14 • texinfo • make • libtool • pkg-config >= 0.23 (or compatible) • libusb-1.0 • libftdi/ libftdi1-dev • libusb-0.1 or libusb-compat-0.1 for some older drivers
Then, I typed the following in Command Line; source sourceme.sh && ./pulp-tools/bin/plpbuild checkout build --p openocd –-stdout
I was facing the following errors, I will share them along with their solution.
Known issue:
1. In function 'memset',
inlined from 'mg_gen_ataid' at src/flash/mflash.c:1162:2,
inlined from 'mg_storage_config' at src/flash/mflash.c:1174:2:
/usr/include/x86_64-linux-gnu/bits/string_fortified.h:71:10: error: '__builtin_memset' offset [509, 512] from the object at 'buff' is out of the bounds of referenced subobject 'reserved7' with type 'mg_io_uint8[186]' {aka 'unsigned char[186]'} at offset 322 [-Werror=array-bounds]
71 | return __builtin___memset_chk (__dest, __ch, __len, __bos0 (__dest)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Go to directory:
/home/c2sd2/pulpissimo/pulp-sdk/tools/riscv-openocd/src/flash/mflash.h
line no 109/110
mg_io_uint8 reserved7[186];
to
mg_io_uint8 reserved7[190];
cLink: https://pulp-platform.org/community/printthread.php?tid=268
2. Configuring PULP SDK at: /home/c2sd2/pulpissimo/pulp-sdk/pkg/sdk/dev
Traceback (most recent call last):
File "./pulp-tools/bin/plpbuild", line 3, in <module>
import plptools as plp
File "/home/c2sd2/pulpissimo/pulp-sdk/pulp-tools/bin/plptools.py", line 21, in <module>
import plpartifactory
File "/home/c2sd2/pulpissimo/pulp-sdk/pulp-tools/bin/plpartifactory.py", line 20, in <module>
from artifactory import ArtifactoryPath
ModuleNotFoundError: No module named 'artifactory'
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# python3 -mpip install -U dohq-artifactory
clink: https://github.com/devopshq/artifactory/issues/105
3. cannot import name 'isoparse' from 'dateutil.parser'
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
pip install python-dateutil --upgrade
https://stackoverflow.com/questions/40809296/upgrade-the-python-package-dateutil-could-not-find-a-version
_______________________________________________________________
4. ModuleNotFoundError: No module named 'twisted'
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
sudo pip3 install twisted
https://stackoverflow.com/questions/47846084/no-module-named-twisted
_______________________________________________________________
5. ModuleNotFoundError: No module named 'openpyxl'
ModuleNotFoundError: No module named 'xlsxwriter'
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
sudo apt-get install python3-openpyxl
python3 -m pip install --user xlsxwriter
https://stackoverflow.com/questions/34509198/no-module-named-openpyxl-python-3-4-ubuntuAfter that I was able to run the following command:
$/home/c2sd2/pulpissimo/pulp-sdk/pkg/openocd/1.0/bin/openocd -f openocd-zedboard-hs2.cfg
Inside pulpissimo-zedboard directory
zealshah29
commented
5 months ago Hello, I am finally able to get the output. Apparently turns out my USB to UART cable was faulty due to which I was not able to get the output.
rtspk
commented
5 months ago @zealshah29 Hello,
My question is unrelated to your post. I am in the process of implementing RISC-V cores on FPGA. Currently, I am trying to run an RTL simulation. So I wanted to ask, which tool version of Mentor Questa SIM did you use to simulate the design?
JTAG and UART Connections:
C Program:
Compiling test.c file in hello with updated frequencies:
loading bitstreams into fpga board:
running openocd:
Output on gdb terminal:
Now I can't see any output on the minicom (3rd terminal)
Can anyone please suggest what can be done? @bluewww @meggiman Thanks!