nikhill-agnisys
commented
3 years ago Closing, as after spending some additional time in target simulation I was able to find why my abstract commands were failing. My SB was indeed tied of, causing debug state to remain as 'SB_CMD_RESP' for rest of the simulation.
Adding crossbar to route the transactions worked for me.
Hello all,
I am trying to debug SweRV RISCV RTL v1.9 during simulation using bitbang bridge and openocd in my environment. For this, I have instantiated SimJTAG module in my testbench and connected it with swerv core. Now, using bitbang a server socket is created and I am able to listen on port 9999.
In another terminal (terminal 2) , I launched openocd (vOpen On-Chip Debugger 0.11.0+dev-01861-g6edf98db7-dirty) using my 'sim_swervjtag.cfg' file, the contents of config file are shown below,
` adapter speed 100
adapter driver remote_bitbang remote_bitbang_host localhost
remote_bitbang_port 9999
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x01
set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME
riscv set_enable_virt2phys off
riscv set_mem_access abstract
riscv expose_csrs 1988
proc swerv_eh1_execute_fence {} {
Execute fence + fence.i via "dmst" register
}
$_TARGETNAME configure -event resume-start { swerv_eh1_execute_fence }
$_TARGETNAME configure -event step-start { swerv_eh1_execute_fence }
init
halt `
On another terminal (terminal 3), When I connect using telnet localhost 4444 and try to issue load_image command after reset I get timeout error as below,
On terminal 2, it outputs as shown without -d debug switch,
With debug switch -d, please find attached the log file 'openocd.log',
openocd.log
I have tried increasing the timeout interval using 'riscv set_command_timeout_sec' to 2000 but then it never comes out.
If possible, please point me to any pointer on how to resolve this. Thanks.