A timeout waiting for an SBA access to complete can be signaled with SBCS[SBERROR] == 1, according to the RISCV debug spec. The timeout value can be set either as an input signal, or as a design constant (parameter), in terms of clock cycles. The dm_sba.sv would then need to implement a counter that flags the timeout error if the response from the bus is not seen within that window.
Without support for this, the debugger will hang indefinitely, if an attempt is made to a peripheral that is inadvertently held in reset or clock-gated without the user's knowledge.
A timeout waiting for an SBA access to complete can be signaled with
SBCS[SBERROR] == 1, according to the RISCV debug spec. The timeout value can be set either as an input signal, or as a design constant (parameter), in terms of clock cycles. Thedm_sba.svwould then need to implement a counter that flags the timeout error if the response from the bus is not seen within that window.Without support for this, the debugger will hang indefinitely, if an attempt is made to a peripheral that is inadvertently held in reset or clock-gated without the user's knowledge.