Prior to this PR, the W1C sberror field of the sbcs CSR only got cleared when 3b'001 was written to it. When other values, e.g., 3b111, were written, the field did not get cleared. This is a mismatch to the RISC-V External Debug Support spec, which states "Writing 1 to every bit clears the field".
This PR fixes that mismatch in a backwards-compatible way, i.e., now any non-zero write to sberror, including 3'b001, clears it. See issue #154 for further information and discussion.
This resolves #154.
This has been tested in OpenTitan with OpenOCD connected to this debug module instantiated on an FPGA to confirm that this solves the problem described in lowRISC/opentitan#17729.
timothytrippel
commented
1 year ago
Prior to this PR, the W1C
sberrorfield of thesbcsCSR only got cleared when3b'001was written to it. When other values, e.g.,3b111, were written, the field did not get cleared. This is a mismatch to the RISC-V External Debug Support spec, which states "Writing 1 to every bit clears the field".This PR fixes that mismatch in a backwards-compatible way, i.e., now any non-zero write to
sberror, including3'b001, clears it. See issue #154 for further information and discussion.This resolves #154.
This has been tested in OpenTitan with OpenOCD connected to this debug module instantiated on an FPGA to confirm that this solves the problem described in lowRISC/opentitan#17729.