The RISC-V spec (v0.13.2, here) defines the dmcontrol.haltreq bit with access "W" (Section 3.12.2), which is defined as "Write-only. When read this field returns 0" (Table 1.2). However, the current implementation allows this bit to be read as 1 after a write sets it to 1.
Any easy fix might be to mask off the top bit of the read value in dm_csrs.sv:
dm::DMControl: resp_queue_inp.data = dmcontrol_q;
The RISC-V spec (v0.13.2, here) defines the dmcontrol.haltreq bit with access "W" (Section 3.12.2), which is defined as "Write-only. When read this field returns 0" (Table 1.2). However, the current implementation allows this bit to be read as 1 after a write sets it to 1.
Any easy fix might be to mask off the top bit of the read value in dm_csrs.sv:
dm::DMControl: resp_queue_inp.data = dmcontrol_q;