Feature request: Support for bus error on SBA interface

[Silabs-ArjanB]

Hello,

Could support for SBA master interface bus errors be added? This would mean the following:

• Addition of master_r_err_i pin on dm_top.sv
• Addition of master_err_i pin on dm_obi_top.sv
• The error input would apply to both reads and writes and would only be considered when the master_r_valid_i signal is high
• In dm_sba.sv the occurrence of a bus error can be signaled with an sberror code of 2 ('a bad address was accessed')