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pulp-platform / riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores
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dmireset can be accidentally triggered #88

Closed Silabs-ArjanB closed 3 years ago

Silabs-ArjanB commented 3 years ago

The dmireset functionality of the dtmcs register is implemented such that it can become triggered by merely shifting the data register even if the intended final value of dtmcs does not have the dmireset bit set.