Closed Silabs-ArjanB closed 3 years ago
A DMI read of SBAddress0 andSBAddress0 will (wrongly) trigger SBBUSYERROR when the system bus master is busy.
https://github.com/pulp-platform/riscv-dbg/blob/f9cf9c40923151afe743fc06b2953731291eae17/src/dm_csrs.sv#L328
According to the RISC-V Debug spec this should only happen for writes:
A DMI read of SBAddress0 andSBAddress0 will (wrongly) trigger SBBUSYERROR when the system bus master is busy.
https://github.com/pulp-platform/riscv-dbg/blob/f9cf9c40923151afe743fc06b2953731291eae17/src/dm_csrs.sv#L328
According to the RISC-V Debug spec this should only happen for writes: