Closed luca-valente closed 3 years ago
Looks like not(synthesys) automatically overrides the fpga target. To have the xilinx-specific cells linked by Bender to Vivado, we need to modify synthesis into asic. Fixed typo in sram cells.
not(synthesys)
fpga
synthesis
asic
Actually, before merging, could you check if #12 also works for you?
Hi @niwis! #12 works for me as well!
Merged via #16. Furthermore, I replaced tag v0.2.55 with v0.2.6
v0.2.55
v0.2.6
Looks like
not(synthesys)
automatically overrides thefpga
target. To have the xilinx-specific cells linked by Bender to Vivado, we need to modifysynthesis
intoasic
. Fixed typo in sram cells.