Clean-up and add generic SRAMs

pulp-platform / tech_cells_generic

Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

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Clean-up and add generic SRAMs #2

Closed zarubaf closed 4 years ago

zarubaf commented 5 years ago

I have cleaned up this repository. Please let me know your input and lets start a discussion.

bluewww commented 4 years ago

Two things

PULPissimo uses 0532e53c1a323db4a55381d123c55bdc4fab06f which is this release branch and it work fine there
On master and gwt there are a few changes to pulp_clock_gating_async.sv. I think they are worthwhile to cherry pick into this branch (Let's just ignore for a moment that this is actually not even a tech cell). The other commits don't look useful.

If no one objects I can do those changes and then from my point of view we can go ahead with the merge.

zarubaf commented 4 years ago

Please go ahead @bluewww Please also fix the maintainer in the README.md to point to you or delete it.

bluewww commented 4 years ago

So I went through all the commits on master and gwt since the fork at b5bdde7c2d9795b484d4470b28c0359885697ee4 again. I was mistaken about the required changes on pulp_clock_gating_async.sv these changes were mostly noise. I will leave it as is.

As for the README.md changes I will leave until after our next meeting regarding this repo.

fabianschuiki commented 4 years ago

Apparently there are some conflicts WRT to master. We should probably do a rebase onto master first, fix any conflicts,then do a merge?

zarubaf commented 4 years ago

@bluewww Did you already re-base this branch somewhere? I'd suggest we factor out the clocking cells. @meggiman Am I correct that the clock cells are the only one you are using?

bluewww commented 4 years ago

I didn't do any rebases yet. Afaik the FPGA ports of PULPissimo use the xilinx RAM wrappers.

meggiman commented 4 years ago

@zarubaf I am using the new clock cells (cells in tc_clk.sv) in my own IP (hd_accelerator, not the smart-wakeup circuit) but I can easily change that if necessary. I did not do any changes to pulp_soc or any other IPs. They are all still using the old (now deprecated) cells. The FPGA port of pulpissimo does not make use of any of the xilinx techcells in this repo. Each FPGA port generates its own LogicoreIP for clock generation and block memory and contains its own implementation of pad_functional* and the clock gating cells used within pulpissimo (e.g. pulp_clock_gating).

anga93 commented 4 years ago

This release branch works fine in PULP.

zarubaf commented 4 years ago

Closing to #3 and #4