This PR adds a new generic clock gate cell (OR-gate) to the tc_clk.sv cell family. Furthermore, I added a warning about the limitations of the tc_clk_mux2 cell in common standard cell libraries. They are not glitch-free and must not be used for dynamic switching between two clocks without any additional precautionary steps.
This PR adds a new generic clock gate cell (OR-gate) to the
tc_clk.svcell family. Furthermore, I added a warning about the limitations of thetc_clk_mux2cell in common standard cell libraries. They are not glitch-free and must not be used for dynamic switching between two clocks without any additional precautionary steps.