tc_clk_xilinx.sv: Add `IS_FUNCTIONAL` parameter on clk_mux

pulp-platform / tech_cells_generic

Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

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tc_clk_xilinx.sv: Add `IS_FUNCTIONAL` parameter on clk_mux #28

Open CyrilKoe opened 1 year ago

CyrilKoe commented 1 year ago

The goal is to disable the default instantiation of the BUFGMUX, as it consumes lots of clock resources when it is not actually needed. It can also create long BUF chains that can fail DRCs. This can often fail Vivado implementations. When buffering is needed, who's instantiating the IP has to explicitly set it.

luca-valente commented 1 year ago

@CyrilKoe We need to add the parameter also in the RTL target file so that it is actually possible to use it. Here as for the clock gating cell.

CyrilKoe commented 1 year ago

@niwis @luca-valente Canged now, if you agree with using this parameter I will start a Carfield CI with the change and I will comment here if it passed.