Add generic SRAM

[WRoenninger]

• Added a generic tc_sram module.
  • parameterizable latency
  • parameterizable simulation initialization
  • can print a configuration message at simulation start
• Added testbench tb_tc_sram with simulation script which tests multiple parametrisations
• Added Bender dependency for common_verification, version 0.2.0
• Added Xilinx Vivado tech dependent tc_sram_xilinx module which implements functionality for single and daul port SRAM with XPM macros, has still to be tested on FPGA

[zarubaf]

Ping @accuminium

[WRoenninger]

Moved the latching of the read output to the same process as the write of the internal memory array. From the Xilinx XPM documentation:

A read operation is implicitly performed to address addr[a|b] combinatorially. The data output
is registered each clk[a|b] cycle that en[a|b] is asserted.

The latch of the read pipeline now takes place before a value gets written to the internal memory array.

[andreaskurth]

I think this makes sense, because it eliminates the combinatorial path from written to read data also in the special case that both addresses are equal.

[zarubaf]

Thanks for following up on this! LGTM

[zarubaf]

Can you also change the README and CHANGELOG, please? Then I am going to merge and release.

[andreaskurth]

@zarubaf Do not forget to rebase before merging to resolve all the fixups @WRoenninger has nicely committed.

[zarubaf]

Merged! Thanks