Closed yo96 closed 4 years ago
Merging #152 into master will increase coverage by
0.02%
. The diff coverage isn/a
.
@@ Coverage Diff @@
## master #152 +/- ##
==========================================
+ Coverage 90.42% 90.45% +0.02%
==========================================
Files 277 279 +2
Lines 23745 23846 +101
==========================================
+ Hits 21472 21570 +98
- Misses 2273 2276 +3
Impacted Files | Coverage Δ | |
---|---|---|
pymtl3/stdlib/connects/connect_bits2bitstruct.py | 93.75% <0.00%> (ø) |
|
...tl3/stdlib/connects/connect_bits2bitstruct_test.py | 100.00% <0.00%> (ø) |
Continue to review full report at Codecov.
Legend - Click here to learn more
Δ = absolute <relative> (impact)
,ø = not affected
,? = missing data
Powered by Codecov. Last update 13c53cf...35f5840. Read the comment docs.
@ptpan can this actually help simplify verilog import?
@jsn1993 Another issue I'd like to discuss is whether we want to check the bitwidth before we do the connect? If so that means we need to call get_nbits
on the bitstruct and as a result we traverse the tree twice. I was wondering if there is a way to avoid the repetitive tree traversal.
@jsn1993 Another issue I'd like to discuss is whether we want to check the bitwidth before we do the connect? If so that means we need to call
get_nbits
on the bitstruct and as a result we traverse the tree twice. I was wondering if there is a way to avoid the repetitive tree traversal.
whatever. I think I'm over optimizing things.
Very small PR that adds
connect_bits2bitstruct
in stdlib and aget_type
API for connectables.