Verilog translation bug fix

[ptpan]

1. Fixed a bug which occurs when a free variable is used as the step of for loop
2. Improved the translated BitStruct file info
3. Added a check which prevents BitStruct fields from using the names of BitStructs

[codecov[bot]]

Codecov Report

Merging #159 into master will increase coverage by 0.03%. The diff coverage is 92.85%.

@@            Coverage Diff             @@
##           master     #159      +/-   ##
==========================================
+ Coverage   89.07%   89.11%   +0.03%     
==========================================
  Files         289      289              
  Lines       24892    24924      +32     
==========================================
+ Hits        22172    22210      +38     
+ Misses       2720     2714       -6

Impacted Files	Coverage Δ
...ilog/translation/test/VTranslator_L2_cases_test.py	56.81% <100%> (+5.53%)	:arrow_up:
.../rtlir/behavioral/test/BehavioralRTLIRPass_test.py	100% <100%> (ø)	:arrow_up:
...passes/backends/verilog/translation/VTranslator.py	97.61% <100%> (+0.21%)	:arrow_up:
pymtl3/passes/rtlir/rtype/RTLIRDataType.py	91.48% <100%> (+1.07%)	:arrow_up:
pymtl3/passes/backends/verilog/errors.py	70.73% <100%> (+2.31%)	:arrow_up:
.../translation/behavioral/VBehavioralTranslatorL2.py	98.03% <75%> (-0.98%)	:arrow_down:
pymtl3/passes/testcases/test_cases.py	85.58% <88.23%> (+0.02%)	:arrow_up:
pymtl3/passes/rtlir/behavioral/BehavioralRTLIR.py	87.12% <0%> (+0.37%)	:arrow_up:
...lir/behavioral/BehavioralRTLIRVisualizationPass.py	65.44% <0%> (+1.29%)	:arrow_up:

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