fix verilator vcd

[jsn1993]

• fix verilator vcd file names when there are multiple verilator imported model
• fix verilator vcd dumping for models without clk signal

[codecov[bot]]

Codecov Report

Merging #193 into master will increase coverage by 0.00%. The diff coverage is 33.33%.

@@           Coverage Diff           @@
##           master     #193   +/-   ##
=======================================
  Coverage   90.36%   90.37%           
=======================================
  Files         311      311           
  Lines       27606    27608    +2     
=======================================
+ Hits        24947    24950    +3     
+ Misses       2659     2658    -1     

Impacted Files	Coverage Δ
...ds/verilog/import_/verilator_wrapper_c_template.py	100.00% <ø> (ø)
...s/verilog/import_/verilator_wrapper_py_template.py	100.00% <ø> (ø)
pymtl3/stdlib/test_utils/test_helpers.py	50.31% <0.00%> (+0.31%)	:arrow_up:
...ends/verilog/import_/VerilogVerilatorImportPass.py	93.66% <100.00%> (+0.01%)	:arrow_up:
pymtl3/passes/sim/PrepareSimPass.py	93.78% <0.00%> (+0.51%)	:arrow_up:

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