Closed ptpan closed 3 years ago
Merging #204 (4addaac) into master (6327bb1) will increase coverage by
0.01%
. The diff coverage is100.00%
.
@@ Coverage Diff @@
## master #204 +/- ##
==========================================
+ Coverage 90.48% 90.50% +0.01%
==========================================
Files 316 316
Lines 27825 27848 +23
==========================================
+ Hits 25178 25203 +25
+ Misses 2647 2645 -2
Impacted Files | Coverage Δ | |
---|---|---|
...kends/verilog/test/TranslationImport_adhoc_test.py | 97.18% <ø> (ø) |
|
...s/verilog/translation/VerilogTranslationConfigs.py | 100.00% <ø> (ø) |
|
...ends/verilog/translation/VerilogTranslationPass.py | 73.17% <ø> (ø) |
|
...kends/generic/structural/StructuralTranslatorL1.py | 86.91% <100.00%> (ø) |
|
...l3/passes/backends/verilog/testcases/test_cases.py | 96.77% <100.00%> (+0.02%) |
:arrow_up: |
.../translation/structural/VStructuralTranslatorL4.py | 84.82% <100.00%> (+0.85%) |
:arrow_up: |
...on/structural/test/VStructuralTranslatorL4_test.py | 100.00% <100.00%> (ø) |
|
pymtl3/passes/testcases/test_cases.py | 86.53% <100.00%> (+0.13%) |
:arrow_up: |
...passes/backends/verilog/translation/VTranslator.py | 95.69% <0.00%> (+1.07%) |
:arrow_up: |
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This PR makes sure explicit_module_name on child components are always honored