Closed ptpan closed 3 years ago
Merging #209 (378d579) into master (2353413) will increase coverage by
0.00%
. The diff coverage is100.00%
.
@@ Coverage Diff @@
## master #209 +/- ##
=======================================
Coverage 90.50% 90.50%
=======================================
Files 316 316
Lines 27875 27879 +4
=======================================
+ Hits 25229 25233 +4
Misses 2646 2646
Impacted Files | Coverage Δ | |
---|---|---|
...sses/backends/verilog/VerilogPlaceholderConfigs.py | 92.68% <100.00%> (ø) |
|
.../translation/structural/VStructuralTranslatorL4.py | 85.34% <100.00%> (+0.52%) |
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Behavior before: a name in the local scope is used while generating sub-component declarations (e.g.,
s.pmx.proc.dmem.req.rdy
->rdy
). This breaks any port map on that component.Current behavior: a full name of port objects is used while generating sub-component declarations. This makes sure the translation pass honors the port map on that sub-component regardless of how many levels of nested interfaces are in it.